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[VHDL-FPGA-Verilog] UART_Transmitter_Arch

Description: 自己编写的带有FIFO的UART串口发送模块，代码通过状态机实现，开发语言是Verilog-I have written to the FIFO UART serial transmit module code through the state machine implementation, development languages ​ ​ Verilog
Platform: | Size: 2048 | Author: wangzhongwei | Hits:

[VHDL-FPGA-Verilog] FIFO_V1

Description: 同步FIFO和异步FIFO程序，希望对大家有用！verilog程序。-Synchronous FIFO and asynchronous FIFO procedures, and hope to be useful! The verilog procedure.
Platform: | Size: 5120 | Author: dean | Hits:

[VHDL-FPGA-Verilog] fifo_uart

Description: uart的verilog代码,包含fifo，并且采用过采样以防止噪声的干扰-uart verilog code
Platform: | Size: 3072 | Author: 李天一 | Hits:

[VHDL-FPGA-Verilog] generic_fifos_latest.tar

Description: fifo的verilog代码，包含rtl，sim，testbench内容的verilog代码，完全可用-rtl code of a fifo
Platform: | Size: 20480 | Author: yy | Hits:

[Parallel Port] fifo2

Description: 一种简单的FIFO的verilog代码，有利于理解FIFO的工作原理-code of fifo in verilog
Platform: | Size: 1024 | Author: 司岚山 | Hits:

[Other] fifo_rd64

Description: 实现64位数据位宽的fifo的功能,用的是verilog代码。-Fifo functionality
Platform: | Size: 2048 | Author: 郭胜 | Hits:

[VHDL-FPGA-Verilog] uart_fifo_design

Description: verilog语言时序的异步读写FIFO，请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
Platform: | Size: 185344 | Author: 张炽 | Hits:

[Parallel Port] CummingsSNUG2002SJ_FIFO1_rev1_1

Description: FIFO设计,采用verilog语言编写，相当不错，验证可行-Altera FPGA CPLD design (Basics) CD-ROM1
Platform: | Size: 132096 | Author: pengqianqian | Hits:

[VHDL-FPGA-Verilog] asyn_fifo_bk

Description: 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
Platform: | Size: 3246080 | Author: 江豪 | Hits:

[VHDL-FPGA-Verilog] prj_5

Description: FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
Platform: | Size: 288768 | Author: amin | Hits:

[VHDL-FPGA-Verilog] FIFOverilog

Description: 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
Platform: | Size: 11264 | Author: 章鱼 | Hits:

[VHDL-FPGA-Verilog] verilog_fifo.tar

Description: Verilog FIFO model independent
Platform: | Size: 164864 | Author: Pradeep | Hits:

[VHDL-FPGA-Verilog] 61EDA_C2212

Description: 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
Platform: | Size: 3584000 | Author: xueyuan | Hits:

[VHDL-FPGA-Verilog] UART_FIFO

Description: Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
Platform: | Size: 702464 | Author: 李子豪 | Hits:

[VHDL-FPGA-Verilog] syn_fifo

Description: 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
Platform: | Size: 1024 | Author: 王敏志 | Hits:

[VHDL-FPGA-Verilog] myuart

Description: 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
Platform: | Size: 492544 | Author: 夏小保 | Hits:

[Communication] exercise3

Description: 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.
Platform: | Size: 1441792 | Author: 董明岩 | Hits:

[VHDL-FPGA-Verilog] VGA800

Description: 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be tested for color stripe.
Platform: | Size: 7909376 | Author: 普尔 | Hits:

[Software Engineering] ht_fifo

Description: fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
Platform: | Size: 126976 | Author: fengsen | Hits:

[VHDL-FPGA-Verilog] 20131010-code

Description: fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
Platform: | Size: 888832 | Author: jianhaoran | Hits:
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